1. Field of the Invention
The present invention relates to a film formation method and apparatus for a semiconductor process for forming a silicon-containing insulating film doped with a metal on a target substrate, such as a semiconductor wafer. The term “semiconductor process” used herein includes various kinds of processes which are performed to manufacture a semiconductor device or a structure having wiring layers, electrodes, and the like to be connected to a semiconductor device, on a target substrate, such as a semiconductor wafer or a glass substrate used for an FPD (Flat Panel Display), e.g., an LCD (Liquid Crystal Display), by forming semiconductor layers, insulating layers, and conductive layers in predetermined patterns on the target substrate.
2. Description of the Related Art
In manufacturing semiconductor devices for constituting semiconductor integrated circuits, a target substrate, such as a semiconductor wafer, is subjected to various processes, such as film formation, etching, oxidation, diffusion, reformation, annealing, and natural oxide film removal. US 2006/0286817 A1 discloses a semiconductor processing method of this kind performed in a vertical heat-processing apparatus (of the so-called batch type). According to this method, semiconductor wafers are first transferred from a wafer cassette onto a vertical wafer boat and supported thereon at intervals in the vertical direction. The wafer cassette can store, e.g., 25 wafers, while the wafer boat can support 30 to 150 wafers. Then, the wafer boat is loaded into a process container from below, and the process container is airtightly closed. Then, a predetermined heat process is performed, while the process conditions, such as process gas flow rate, process pressure, and process temperature, are controlled.
Nonvolatile memory devices are known as semiconductor integrated circuits of this kind. The nonvolatile memory devices encompass floating gate type memory devices including a floating gate and SONOS type memory devices including an electric charge trap layer (Jpn. Pat. Appln. KOKAI Publication No. 2006-229233). Recently, SONOS type memory devices including an electric charge trap layer have attracted attention, because they are relatively well operated in writing and erasing. A SONOS type memory device has a structure in which a silicon oxide film, an electric charge trap layer formed of a silicon nitride film, and a silicon oxide film are interposed between a semiconductor substrate, such as a silicon substrate, and a gate electrode made of, e.g., poly-silicon.
The electric charge trap layer is formed of a metal-doped film, which is a silicon nitride film (SiN film) doped with a metal, such as aluminum. Where a memory device includes such a film doped with a metal, the memory device is improved in some of the operational characteristics, such as writing, erasing, and retention.
For example, as a method for forming a metal-doped film of this kind, there is a method using a CVD (Chemical Vapor Deposition) method arranged to simultaneously supply film formation gases for forming an SiN film and a gas containing the metal into a process container. Further, there is a method for forming a film having a predetermined thickness, by alternately and intermittently supplying film formation gases to repeatedly laminate very thin layers each having an atomic or molecular level thickness one by one (for example, Jpn. Pat. Appln. KOKAI Publications No. 6-45256 and No. 11-087341). In general, this film formation method is called ALD (Atomic layer Deposition) or MLD (Molecular Layer Deposition), which allows a predetermined process to be performed without exposing wafers to a very high temperature.
Incidentally, in metal-doped films of this kind, the metal concentration in the film and the concentration distribution in the film thickness direction exert large influences on some of the characteristics of the metal-doped films. However, conventional methods described above for forming a metal-doped film tend to cause the metal concentration to be relatively higher, and thus entails a difficultly in setting the metal concentration to be relatively lower with high controllability. In this case, the electrical characteristic of the metal-doped film cannot be sufficiently improved. Particularly, in recent years, owing to the demands of increased miniaturization and integration of semiconductor integrated circuits, the problem described above needs to be solved.